Japanese Patent No. 4735235 (hereinafter referred to as “Patent Document 1”) discloses a semiconductor device including a semiconductor substrate in which an element region and a termination region located outside of the element region are provided. The element region includes: a gate trench; a gate insulating film covering an inner surface of the gate trench; and a gate electrode located inside of the gate insulating film. The termination region includes: a termination trench; and a termination insulating layer filling an inner part of the termination trench and covering an upper surface of the semiconductor substrate. A gate wiring electrically connected to the gate electrode is disposed at an upper surface of the termination insulating layer.